1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including complementary MOSFETs having both an n-ch MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a p-ch MOSFET on the same substrate, and in particular, to a method of manufacturing a dual-gate CMOS device which consists of an n-ch MOSFET having an n-type impurities doped polysilicon gate and a p-ch MOSFET having a p-type impurities doped polysilicon gate.
2. Description of the Prior Art
Conventionally, a gate electrode of complementary MOSFETs has been formed by patterning polysilicon film after doping by ion implanting and/or solid-phase diffusing n-type impurities (n-type dopant) such as phosphorous (hereinafter, referred as "P") or arsenic (hereinafter, referred as "As") into a polysilicon film. In this case, the n-ch MOSFET is formed as a surface channel type and the p-ch MOSFET is formed as a buried channel type.
Specifically, the prior art complementary MOSFETs have a structure in which gate electrodes of both the n-ch MOSFET and the P-ch MOSFET are of n-type, and in the n-ch MOSFET, a source and a drain are of n-type, and in the p-ch MOSFET, a source and a drain are of p-type.
However, recently, semiconductor devices have been progressed in making finer and higher in integration, and as a result, elements have also been made finer. For example, fine MOSFETs having a gate length of 0.5 .mu.m or less have been used.
In the fine MOSFETs, it is essential to suppress the short channel effect. For this reason, the gate electrode of the p-ch MOSFET is made p-type, and the surface channel type p-ch MOSFET which has higher capability of suppressing the short channel effect than the buried channel MOSFET has been used.
In the prior art complementary MOSFETs, techniques for forming both the n-ch MOSFET and the p-ch MOSFET as the surface type are proposed, for example, by Bijan Davari et al. in "IEEE Transaction on Electron Devices", Vol. 39, p 967, 1992, and by Wen Lin et al. in "Solid-State Electronics", Vol. 32, p 965, 1989.
These techniques include the following processes.
First, after forming a polysilicon film which is a gate electrode forming material, this film is patterned to form a gate electrode. Subsequently, n-type impurities are ion implanted selectively into a region in which an n-ch MOSFET is to be formed thererby to form an n-type gate electrode, and n-type source and drain.
Thereafter, p-type impurities are ion implanted selectively into a region in which a p-ch MOSFET is to be formed thereby to form a p-type gate electrode, and p-type source and drain.
Specifically, in both the p-ch MOSFET and n-ch MOSFET, the ion implantation to form the source and drain, and the ion-implantation of impurities to reduce a resistance of the gate electrode are simultaneously performed.
The advantage is provided in that in both the MOSFETs, the surface impurity concentration is sufficiently high in the source and drain, and shallow junctions are formed in the source and drain.
However, in the technique to form the channels of both the MOSFETs as being of the surface type, there is a problem in that although the shallow junctions are formed in the source and drain, the carrier concentration in the gate electrode becomes low. As a result, when a low voltage is applied to the gate electrode of the MOSFET, the transconductance and the sub-threshold characteristic of the MOSFET are degraded.
This is caused by the fact that the activation ratio of the impurities in the polysilicon film is 1/10 to 1/100 of the activation ratio of the impurities in the monocrystalline silicon film.
Accordingly, for example, when the impurities having a concentration of about 1.times.10.sup.15 /cm.sup.2 are ion implanted to the gate electrode and the source and drain, in the source and drain, the carrier concentration is about 1.times.20.sup.20 /cm.sup.3, whereas in the gate electrode, it is about 1.times.10.sup.19 /cm.sup.3. Here, for example, when the gate oxide film has a film thickness of 7 nm, the carrier concentration required for the gate electrode is 1.times.20.sup.20 /cm.sup.3 or more. If the carrier concentration of the gate electrode is less than this value, during the operation of the MOSFET under a low gate voltage, an electrical depletion layer will be caused in an interface between the gate oxide film and the gate electrode (polysilicon film), and a problem is posed in that the transconductance of the MOSFET is reduced to a great extent and the sub-threshold characteristic is deteriorated.
Furthermore, the inventors of the present application discovered that in the case of the gate oxide with a polysilicon electrode having a low dopant concentration, the initial breakdown voltage is abnormally reduced.
Specifically, when a MOS capacitor having an area of 4 mm.sup.2 is formed in the process in which first, a gate-electrode-forming polysilicon film of about 150 nm in film thickness is formed on a gate oxide film of about 8 nm in film thickness, and then, boron difluoride (hereinafter, referred to as "BF.sub.2 ") ions are implanted into the polysilicon film with a concentration of 1.times.10.sup.15 /cm.sup.2, and then, the ion-implanted polysilicon film is activated, the frequency of having the intrinsic breakdown voltage of the MOS capacitor was about 22% of the total number. On the other hand, in a polysilicon film in which the BF.sub.2 ions are implanted with a concentration of 1.times.10.sup.16 /cm.sup.2, the above-mentioned frequency was about 98%. This is because that in the polysilicon film of low impurity concentration, the growth of crystal grain was insufficient.
Accordingly, various methods have been considered.
(1) A method in which in order to improve the activation of the impurities implanted into the gate electrode (polysilicon film), the amount of ion-implantation of impurities is increased, and to activate the impurities, the temperature of a thermal treatment is increased. PA1 (2) A method in which in addition to the impurities ion-implantation process for forming the source and drain, impurities are ion implanted selectively to the gate electrode thereby to increase the carrier concentration of the gate electrode. PA1 (3) A method in which, as disclosed in Japanese Patent Laid-Open Publication Hei No. 3-290924, an amorphous silicon film is formed on a quartz substrate, and after patterning this film, a thermal treatment at 500.degree. C. for 20 hours, and a further thermal treatment at 1020.degree. C. for 2 hours are carried out in an inactive gas to increase the crystal grain size of the silicon film to a large grain size of about 2 to 3 .mu.m thereby to improve the activation of the impurities in the silicon film. PA1 (4) A method in which, as disclosed in Japanese Patent Laid-Open Publication Hei No. 4-152624, an amorphous silicon film is formed on a quartz substrate, and after patterning this film, the amorphous silicon film is crystallized in oxygen atmosphere of 99.99% or more to have a large grain size of the silicon film of about 2 .mu.m thereby to improve the activation of the impurities in the silicon film.
However, in the method (1), since the amount of ion-implantation of the impurities is increased, or the temperature of the thermal treatment is increased, there is a problem in that the junctions of the source and drain become deep, and the short channel effect is caused so that it cannot be applied to fine MOSFETs. Furthermore, when the thickness of the gate oxide film is as thin as 100 .ANG. or less, and when boron which is the p-type impurity is contained with a high concentration, there is a problem in that the boron penetrates the gate oxide film and reaches the silicon substrate. As a method of preventing this defects, it has been tried to use a silicon oxynitride film which is formed by oxidizing the silicon in N.sub.2 O atmosphere as the gate insulating film.
Furthermore, in the method (2), since the impurity ions of p-type or n-type are selectively implanted into the gate electrode, a problem is posed in that in each of the masking process and the ion implantation process, two processes are increased and the productivity is reduced to a great extent.
Recently, polysilicon thin film transistors have been developed for use as a driver of a liquid crystal display and a load transistor of a high integrated SRAM cell. In order to improve the performance, trials have been conducted to improve the mobility of carriers in the polysilicon. One trial is to subject an amorphous silicon formed on an insulating substrate to a thermal treatment to transform the amorphous silicon into a polysilicon having a relatively large crystal grain size so as to improve the mobility of the carriers.
However, in the method (3), there is a problem in that it takes a too long thermal treatment time, and it lacks the mass-productivity. A further problem is involved in that when the line width is decreased to 1 um or less, it is impossible to increase the crystal grain size, and the activity of the impurities cannot be improved.
Also in the method (4), although the activation ratio of the impurities is improved to that equivalent to a monocrystalline silicon film, since the oxygen concentration at the time of crystallization is high, the surface of the silicon film is oxidized and doped impurities are absorbed in oxide film. Accordingly, a problem is involved in that the activation of the impurities is decreased.